1. Field
The present disclosure relates to electronic integrated circuits (“ICs”), and more specifically to RF power amplifiers (“PAs”).
2. Description of Related Art
Most radio transceivers, such as cell phones that are a ubiquitous feature of modern life, require an RF PA circuit to boost the transmit signal to a level sufficient to be received by a target transceiver, such as a cellular base station. The performance of the RF power amplifier strongly impacts cell phone features such as battery life, operational range and signal quality. Designs that increase signal quality and transmit power generally increase operational range. However, unless the PA power efficiency is also increased, such designs may negatively impact battery life and cost of the cell phone.
Increases in PA power efficiency generally enable improvements in battery life for a selected level of signal quality and operational range. Because removing waste heat incurs costs, improved efficiency generally reduces the costs incurred by removing waste heat. Power efficiency is thus one aspect of the overall cost efficiency of an RF PA designed for a given level of performance. Other aspects of cost efficiency, such as integrated circuit size and other manufacturing considerations, should be concurrently addressed to result in an RF PA that provides the best overall value to a user.
In order to provide high-power capability, a PA circuit requires transistor circuits wherein the transistors have a large total gate width Wg (i.e., the gate dimension that is perpendicular to current flow). For example, effective gate widths greater than 100 mm may be required to obtain a desired power-handling capability. However, for a transistor to have gain at high RF frequencies, the gate length Lg (i.e., the gate dimension parallel to current flow), must be made very small (typically sub-micrometer). This causes a large gate resistance per unit gate width. Typically, when a single RF transistor's gate width exceeds a few tens of micrometers, or the ratio Wg/Lg is >10, the gate resistance begins to degrade the performance of the transistor. To overcome this problem, PA IC designers employ circuits having a plurality of shorter gate-width transistors operably coupled in parallel. A first method of implementing parallel transistor circuits uses interdigitated transistor devices. One exemplary reference relating to interdigitated RF transistors is a technical paper entitled “RFCMOS Unit Width Optimization Technique,” A. F. Tong, et al., IEEE Transactions on Microwave Theory and Techniques, Vol. 55, No. 9, September 2007. This reference is hereby fully incorporated by reference herein, as though set forth in full, for its teachings on interdigitated transistors. A second method of implementing parallel transistor circuits is implemented by connecting transistor devices (which may be interdigitated) in parallel via interconnects and bus lines. Using these methods, PA ICs can be fabricated using a plurality of transistors having small gate lengths and widths, coupled in parallel circuits to provide a power-handling capability corresponding to the sum of the gate widths of the plurality of transistors. To increase voltage handling capability, series circuits of transistors are also employed.
When transistor devices are coupled together in order to increase the power-handling capability of PA ICs, attention must be given to minimizing the parasitic resistances and capacitances caused by interconnects and bus lines. Novel PA ICs are needed to reduce such parasitic resistances and capacitances, thereby providing improvements in power efficiency. Novel PA ICs that provide improvements in removing heat generated by the plurality of transistor devices are needed. Further, novel PA ICs that reduce the overall size of PA ICs, providing improved economy of fabrication are needed. The teachings hereinbelow disclose novel PA ICs and methods of RF amplification that provide solutions to the above-described problems.